1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to scan elements used to provide access for testing integrated circuits.
2. Description of the Related Art
Scan testing is one of a number of different methods available for testing integrated circuits (IC's). Scan testing may be conducted using one or more internal scan chains each of which includes a plurality of serially coupled scan elements. A scan chain may be thought of as a serial shift register. A string of bits comprising test stimulus data may be input into a given scan chain of an IC by shifting each bit from one scan element to the next until each bit has reached its target element. Similarly, captured test result data may be shifted from the IC by shifting each bit of test result data from one scan element in the chain to the next until all bits of the test result data have been shifted into a test system or other receiving device. Shift operations may be synchronized using one or more scan clock signals, which may be separate from the one or more operational clock signals used by the IC during normal operations.
Each scan element may include a functional flop that is configured to perform operations during normal operation of the IC, as well as a scan flop. After test stimulus data has been shifted to a given scan element, it may be input into the functional flop through its corresponding scan flop. During testing, the functional flop may apply the test stimulus data to circuits connected thereto responsive to one or more cycles of an operational clock signal. The functional flop may also be coupled to receive test result data from other circuits coupled thereto. The scan element may capture the test result data upon the completion of testing, after which it may be shifted from the IC as described above.